Recently, a renewed interest in thin-film magnetic random access memories (MRAM) has been sparked by the potential application of MRAM to both nonvolatile and volatile memories. FIG. 1A depicts a portion of a conventional MRAM 1. The portion of the conventional MRAM 1 depicted is at the intersection of two interconnects 20 and 22. Interconnect 20, which is located beneath and isolated from the MTJ stack 10, is commonly referred to as the write word line, and line 22, which is located above and connected to the MTJ device, is commonly referred to as the bit line.
The conventional MRAM 1 includes a number of conventional magnetic elements, one of which is depicted in FIG. 1A. The conventional magnetic element depicted in FIG. 1A is an MTJ stack 30. The MTJ stack 30 thus serves as at least part of a magnetic memory cell. The MRAM 1 also includes an isolation transistor 10 having a source 13, a drain 14, and a gate 16. The source 13 is connected to a ground line 17 via a conductive plug 15. The drain 14 is coupled with the MTJ stack 30 through the use of a conductive stud 18 and a bottom electrode 19. In such a conventional MRAM 1, the memory cells are programmed by magnetic fields induced by current carried in the lines 20 and 22, which are typically copper lines or aluminum lines. Typically, two orthogonal interconnects 20 and 22 are employed. One interconnect, the conventional bit line 22, is positioned above the MTJ stack 30. The second interconnect, the conventional write word line 20, is positioned below the MTJ stack 30.
The MTJ stack 30 is located at the intersection of the conventional bit line 22 and the conventional write word line 20. The MTJ stack 30 primarily includes a free layer 38 having a changeable magnetic vector (not explicitly shown), a pinned layer 34 having a fixed magnetic vector (not explicitly shown), and an insulator 36 in between the two magnetic layers 34 and 38. The MTJ stack 30 also typically includes layers 32 that include seed layers and an anti-ferromagnetic layer that is strongly coupled to the pinned layer 34.
During writing, a first current in the conventional bit line 22 and a second current in the conventional write word line 20 yield two magnetic fields on the free layer 38. In response to these external magnetic fields, the magnetic vector in the free layer 38 orients in a direction that depends on the direction and amplitude of the currents in the conventional bit line 22 and the conventional write word line 20. In general, the direction of the current in the conventional bit line 22 for writing a zero (0) differs from the direction of current in the conventional bit line 22 for writing a one (1). During reading, the transistor 10 is turned on so that a small tunneling current flows from the conventional bit line 22 through the MTJ stack 30 and the isolation transistor 10 to the ground line 17. The amount of current flowing through MTJ stack 30 or the voltage drop across MTJ stack 30 can be measured to determine the state of the memory cell. In some designs, the isolation transistor 10 is replaced by a diode or completely omitted, so that the MTJ stack 30 is in direct contact with conventional write word line 20.
FIG. 1B depicts a high-level flow chart of a conventional method 50 for providing a conventional MRAM, such as the conventional MRAM 1. The method 50 is thus discussed in conjunction with the conventional MRAM 1 depicted in FIG. 1A. Referring to FIGS. 1A and 1B, the isolation transistor 10 is first fabricated, via step 52. The ground line 17, the conventional write word line 20, and the stud 18 are formed, via step 54. Step 54, of forming the ground line 17, the conventional write word line 20, and the stud 18 typically includes multiple sub-steps. The last sub-step of forming the conventional write word line 20 and the stud 18 involves a chemical mechanical polishing (CMP) process to obtain a smooth and flat surface. Once formation of the structures 17, 18, and 20 is completed, a thin dielectric layer is deposited to insulate the conventional write word line 20 from the bottom electrode 19 (which is not formed yet), via step 56. A via is opened to expose the top surface of the stud 18, via step 58. The bottom electrode 19 and the MTJ stack 30 are deposited, via step 60. Thus, the MTJ stack is in electrical contact with the stud 18 through the bottom electrode 19. A photolithography process and an etching process are then carried out to define the dimension of bottom electrode 19, via step 62. Another photolithography and etching process follows to define the dimension of MTJ stack 30, via step 64. The conventional bit line 22 is then formed after any exposed portion of the bottom electrode 19 has been covered by an insulator, via step 66. The conventional bit line 22 is so formed to ensure that the conventional bit line 22 is electrically connected to the stud 18 through the MTJ stack 30. Thus, the conventional MRAM 1 is formed.
FIG. 2 depicts another conventional MRAM 1′. Portions of the MRAM 1′ are analogous to the MRAM 1 and are thus labeled similarly. For clarity, only the MTJ stack 30, the conventional bit line 22′ and the conventional word line 20′ are depicted. The conventional bit line 22′ includes a nonmagnetic portion 25 and magnetic cladding 27. Similarly, the conventional word line 20′ includes a nonmagnetic portion 21 and magnetic cladding 23. The magnetic cladding 23 and 27 are soft magnetic materials, reside on surfaces not facing the MTJ stack 30, and are used to concentrate the magnetic flux associated with the current provided through the conventional word line 20′ and the conventional bit line 22′. Thus, the soft magnetic cladding 23 and 27 concentrate the flux on the MTJ stack 30, making the free layer 38 easier to program. However, one of ordinary skill in the art will readily recognize that the magnetic properties of the portions of the magnetic cladding 23 and 27 on the vertical sidewalls of the conventional lines 20′ and 22′, respectively, are hard to control.
Although the method 50 and conventional MRAMs 1 and 1′ function, one of ordinary skill in the art will readily recognize that the method 50 can lead to a number of faults in the conventional MRAMs 1 and 1′. One of ordinary skill in the art will readily recognize that photolithography process used in defining the MTJ stack 30 in step 64 is carried out on a surface having a complicated topography. In particular, the surface on which the MTJ stack is formed includes a via (not explicitly shown) on top of the stud 18 and a multilayer stack of layers 32, 34, 36, and 38 in the MTJ 30 that resides on the bottom electrode 19. Furthermore, one of ordinary skill in the art will readily recognize that the bottom electrode 19 has a shape that is not flat. One of ordinary skill in the art will, therefore, readily recognize that critical dimension control is very difficult for a photolithography process preformed on a surface that is not flat. As a result, the dimensions of the MTJ stack 30 could vary from place to place along the stack 30 and between different MTJ stacks (not shown). As a result, a significant variation in magnetic performance between magnetic memory cells in the MRAM 1 or 1′ occurs.
Accordingly, what is needed is a method and system for reducing the variation in magnetic performance between magnetic memory cells in the MRAM 1 or 1′.